The present invention generally relates to technologies for signal transmission between devices such as a multiprocessor and a memory in an information processor (e.g., between digital circuits formed of, for example, CMOSs or between the functional blocks using the same), and particularly to a fast bus transmission technology for high-speed data transfer through a bus between a plurality of LSIs connected on the same transmission line.
As a bus system for fast data transfer between a number of nodes as in the multiprocessor, there is an SSTL (Stub Series terminated Transceiver Logic) (EIA/JESD8-8) interface based on JEDEC (Joint Electron Device Engineering Council) standard. This interface, as shown in FIG. 2, is a bus system for use in transmission between LSIs that include input/output interfaces having receivers 21xcx9c25 for receiving data and drivers 11xcx9c15 for transmitting data. A data bus line (main line) 3 is terminated at both ends with a terminal resistor Rtt for matching so that the reflection at both ends can be removed. In addition, matching resistors 31xcx9c35 are respectively provided on stub lines 61xcx9c65 that connect the main line 3 and the interface circuits. The matching resistors 31xcx9c35 act to suppress the reflected waves due to impedance mismatching between the main line and the associated stub line when one of the drivers 11xcx9c15 transmits data.
In the SSTL interface shown in FIG. 2, however, a reflected wave due to impedance mismatching occurs on the signal waveform propagated on the main line 3, disturbing high-speed operation. That is, for example, in FIG. 2, when data is transmitted from driver 11 to receiver 25, the signal waveform from the driver 11 passes through the stub 61 and matching resistor 31 and arrives at the main line 3. In general, the resistance value of the matching resistor 31 can be determined from the characteristic impedance Zo of stub 61 and the characteristic impedance Zoxe2x80x2 of main line 3 as given by the following equation (1).
Rm=Zoxe2x88x92Zoxe2x80x2/2xe2x80x83xe2x80x83(1)
where Rm is the matching resistance 31. The equation (1) is the matching termination condition viewed from the stub side toward the main line. If the characteristic impedances Zoxe2x80x2, Zo of main line 3 and stub 61 are, for example, 50xcexa9, respectively, Rm is determined as 25xcexa9=50xe2x88x9250/2.
On the other hand, the signal waveform transmitted from the driver 11 and arrived at the main line 3 further propagates to the left and right on the main line 3. The waveform that progresses to the left terminates at the terminal resistor Rtt and thus there is no reflected wave. However, the signal to the right passes branch points 52xcx9c55. The reflection coefficient xcex93 at the branch point 52 is given by the following equation (2).
xcex93=(Z1xe2x88x92Zo)/(Z1+Zo)xe2x80x83xe2x80x83(2)
where Z1 is the resultant impedance of the stub 62 including the main line 3 and matching resistor 32, and given by the following equation (3).
Z1=(Zoxe2x80x2(Rm+Zo))/(Zoxe2x80x2+Rm+Zo)=30xcexa9xe2x80x83xe2x80x83(3)
Thus, since the reflection coefficient xcex93 is 0.25 at branch point 52, 25% of the signal power is reflected at the point.
In other words, when the data from the driver 11 passes each of the branches on the main line 3, 25% of the data is reflected at each branch and superimposed on the data. Since this reflected wave occurs during the round trip propagation delay of stub 61xcx9c65, it is necessary to limit the stub line length in order that noise can be reduced for fast transmission. That is, a great restriction is imposed on the interface structure.
It is a first object of the invention to reduce the disturbances of impedance at these branch points, thereby decreasing the noise due to the reflected waves. Thus, it is possible to make much faster operation than SSTL.
It is a second object of the invention to reduce the restrictions on the stub line lengths from the LSI to each blanch point on the main line. Thus, it is possible to provide a greater freedom to the interface structure than SSTL.
It is a third object of the invention to incorporate the terminal resistors necessary for the high-speed bus within the LSIs instead of those on the main line, thereby reducing the mounting area.
The terminal resistors are built in the interface circuits of the LSIs so that the signals propagated on the stub lines can be prevented from being reflected from the interfaces. In addition, variable resistance elements are connected in series with the lines from each of the branch points on the main line. When the LSI receives data or does not transmit/receive data, the variable resistance element connected to the stub line with the LSI joined is made to be ⅓ of the characteristic impedance Zo of the line. When the LSI works as a driver, the variable resistance element connected through that stub line to the LSI is made to have a value of as low as about 5xcexa9 or below, the resistance element connected to the main line is set to have a low value, and the other resistance element is matched with the characteristic impedance Zo of the line.
Thus, when the LSI receives data or does not transmit/receive data, at the branch point, all lines appears to be completely matching-terminated since the resistance elements connected through the stub lines to the LSIs are set to be ⅓ of the characteristic impedance of the line. Therefore, since there is no reflection at the branch point, data can be transferred without noise.
In addition, when the LSI works as a driver, since the variable resistance element connected through the stub line to the LSI is set to have a value of as low as about 1xcexa9, the element connected to the main line to have a low value and the other element to have the characteristic impedance of the line, about 80% of data can be propagated from the driver to the main line, and about 40% of the data, when transmitted to the other variable resistor, can be propagated with no reflection, thus the signal level being kept large enough.